The present invention relates to a logic circuit functioning as a flip-flop.
Use of the gate array has successfully reduced the design period of custom-circuit LSIs to anywhere from two or three months. The gate array is a semiconductor chip having a great number of logic cells, e.g., 2-input NAND or NOR gates, which cells are arrayed in a matrix fashion over a sufficient area of the chip.
To implement a custom-circuit logic function on a chip, a designer (as a user) selects an appropriate gate array from among various types of gate arrays, and interconnects logic cells with a dedicated metal pattern on the gate array chip. Therefore, with the omission of the design work of the semiconductor chip, the bulk of his design work for LSI development merely entails the laying out of the metal pattern for interconnecting the logic cells. Thus, the design period is greatly shortened, compared to that of the LSIs not having gate arrays.
The gate arrays, which are commercially available, serve as base components in designing and manufacturing custom-circuit LSIs. For this reason, the design cost can be shared among the users, resulting in an overall cost reduction of the LSIs. This cost reduction resulting from the use of gate arrays becomes effective in the production of from 2,000 to 3,000 or more LSIs.
The gate array suffers from the following defects, however. First, the integration density of the logic cells on the gate array chip is low, due to the need to ensure the flexibility of the interconnection. Also, a redundancy in the length of the metal pattern must be accepted in designing the custom-circuit LSIs. This redundancy impairs the operational speed of the custom-circuit LSIs.
In a defect inspection of newly manufactured custom-circuit LSIs, test data is applied to the custom-circuit LSIs on the chips, to check a circuit response. In cases wherein custom-circuit LSIs contain a number of flip-flops, such as CPUs, various items of test data must be prepared for the LSIs' defect inspection. Therefore, since the test data is structurally complex, the preparation of such data imposes heavy and troublesome work on the designers.
To lighten the load of testing requirements, one approach used is the so called LSSD (level sensitive scan design), in which a plurality of flip-flops are operated as a shift register at the time of the defect inspection. This approach requires a number of additional lines and circuit elements, however. Therefore, when the LSSD circuit is formed on a gate array chip bearing logic cells with a low integration density, the need for a great number of components restrains the effective chip area; and, thus, might possibly render the metal pattern even more rendundant.